Refer to FIG. 1, which illustrates a conventional differential to single ended converting circuit. The differential to single ended converting circuit comprises a first p type transistor mp1, having a source connected to a voltage source Vdd, a gate and a drain which are connected to each other, a first n type transistor mn1, having a drain connected to the drain of the first p type transistor mp1, and a source connected a current source I, a second p type transistor mp2, having a source connected to the voltage source Vdd, a gate and a drain which are connected to each other, and a second n type transistor mn2, having a drain connected to the drain of the first p type transistor mp2. In addition, the gate of the first n type transistor mn1 and the gate of the second n type transistor mn2 are coupled to differential signals Vin and Vinb respectively.
The differential to single ended converting circuit further comprises a third p type transistor mp3, having a source connected to the voltage source Vdd, and a gate connected to the gate of the first p type transistor mp1 so that a first current mirror (mp1 and mp3) is formed, a third n type transistor mn3, having a drain and a gate both connected to the drain of third p type transistor mp3, and a source connected to a ground, a fourth p type transistor mp4, having a source connected to the voltage source Vdd, and a gate connected to the gate of the second p type transistor mp2 so that a second current mirror (mp2 and mp4) is formed, and a fourth n type transistor mn4, having a drain connected to the drain of the fourth p type transistor mp4, a gate connected to the ground, and a gate connected to the gate of the third n type transistor mn3 so that a third current mirror (mn3 and mn4) is formed. In addition, a parasitic capacitor Cp is coupled to the drain of the fourth n type transistor mn4 and the ground, and the drain of the fourth n type transistor mn4 is as the output terminal Vout of the differential to single ended signal converting circuit
When the differential signals Vin, Vinb is inputted, the currents in and ip flow through the first n type transistor mn1 and the second n type transistor mn2 respectively as shown in FIG. 1. The first p type transistor mp1 and the third p type transistor mp3 form the first current mirror, the second p type transistor mp2 and the fourth p type transistor mp4 form the second current mirror, and the third n type transistor and the fourth n type transistor form the third current mirror, the output current from the output terminal Vout is therefore in plus ip.
The circuit in FIG. 1 is a differential current to voltage converting circuit. Moreover, the differential current in flows through the third p type transistor mp3, the third n type transistor mn3, and the fourth n type transistor mn4 while the differential current ip only flows through the fourth p type transistor mp4. The different numbers of transistor the differential currents in and ip flow leads to the mismatch of the differential currents in and ip which results in jitter and common-mode drift of the output voltage Vout. In addition, to operate the converting circuit operated in high speed, GHz frequency, diode connected transistors, i.e. the first p type transistor mp1, the second p type transistor mp2, and the third n type transistor mp3 must be prevented from turning off. And the first p type transistor mp1, the second p type transistor mp2 and the third n type transistor mn3 require larger size and higher transconductance, i.e. higher gmp1, gmp2 and gmn3.
Moreover, U.S. Pat. No. 6,717,474 discloses a high-speed differential to single-ended converter. Refer to FIG. 2, which illustrates a conventional differential to single ended converter. A differential voltage signal (Vin,Vinb) is provided to a first stage circuit which is comprised of M1, M2, M3 and M4 and a differential current signal (I1 and I2) is obtained. In addition, a second stage circuit comprises a current mirror and a buffer circuit so that the differential current signal (I1 and I2) is converted to an single ended current signal I3 which is I1 plus I2. At last, a single ended current signal I3 is provided to a third stage circuit, a trans-impedance circuit, so that the single ended current signal I3 is converted to a output voltage Vout.
The ninth transistor M9 is a diode connected transistor as shown in FIG. 2. To prevent the ninth transistor M9 from turning off, the differential current signal (I1 and I2) when switing are prevented from being zero. Therefore, a resistor Re is added in the first stage circuit so that the differential current signal (I1 and I2) would not be zero when switching.
Moreover, high input impedance is transferred to low output impedance by the seventh transistor M7 and the eighth transistor M8 of the second stage circuit to enhance the operation speed. In addition, the bias voltage Vb3 is to be adjusted with caution because the seventh transistor M7 and the eighth transistor M8 are for providing high transconductance gm7, gm8 respectively.
Furthermore, the dc bias of the output terminal of the second stage circuit is ⅔ VDD because there are three transistors connected from the voltage source VDD to the ground GND, while the transition point of the input terminal of the third stage circuit is ½ VDD. Hence, the distortion of the output voltage Vout occurs after the second stage circuit and the third stage circuit are connected.
What is more, U.S. Pat. No. 7,053,671 discloses a low-jitter differential-to-single-ended data conversion circuit. Refer to FIG. 3, which illustrates a low-jitter differential-to-single-ended data conversion circuit. The first p type transistor mp1 and the second p type transistor mp2 of FIG. 1 are replaced with resistors Rd as shown in FIG. 3 to effectively lower impedance value. Besides, the transistor 62 is connected to a load device, i.e. transistor 68.
To prevent the transistor 62 which is a diode connected transistor from being turned off, a voltage source Vcc is connected to the gate of the transistor 62 by way of the transistor 68, i.e. the load device. The transistor 62 is thus prevented from turning off so that the operation speed of the conversion circuit is up, However, the conversion circuit which comprises the load device requires more power consumption.